Essential principles and techniques for debugging FPGA hardware circuits

In order to reduce the debugging time and prevent the malfunction of the circuit, you must follow the necessary principles and techniques when debugging the FPGA circuit. In general, refer to the following steps to perform debugging of the FPGA hardware system.

1. Before soldering the hardware circuit, first test whether the power supply and the ground are short-circuited between the power supplies of the circuit board; it is better to test each board so that if the power supply and ground short-circuit occur after the board is soldered, You can first rule out the problem of the board itself.

2. When soldering hardware, first solder the power supply part, then test, eliminate the short circuit of the power supply, etc., whether the power-on measurement voltage is correct; for some circuits with higher power supply requirements, test whether the output voltage of the power chip is working normally. Within the scope of the request.

3. Then solder the FPGA and related download circuits. Once again, measure whether there is a short circuit between the power supply grounds. Check whether the voltages are correct after power-on test. If the static electricity is removed, touch the FPGA to see if it is hot.

a. If a short circuit occurs, it is usually caused by a short circuit of the decoupling capacitor, so the decoupling capacitor is usually not soldered first during soldering. Pin sticking of the FPGA may also cause a short circuit. In this case, you need to compare the circuit diagram and soldering to find out if there is any pin adhesion.

b. If the voltage value is wrong, it is usually caused by the welding fault of the peripheral voltage regulating resistor of the power chip or the insufficient carrying capacity of the power supply. In the latter case, you need to replace the power module with a stronger load capacity. If the I/O pin of the FPGA is stuck to the power pin, the voltage value may be wrong.

c. If the FPGA is hot, there is usually a bus collision. In this case, it is necessary to check whether the peripheral bus may have competition problems. In particular, the multi-chip memory shares the bus time. For example, SRAM and FLASH chips multiplex a bus, and if the chip select signal is valid at the same time, a bus conflict occurs.

4. After the above is completed, the circuit board will run electrically. Connect the download line to the JTAG port to see if the FPGA is detected correctly.

5. Write the test program to the SRAM and PROM respectively to determine if the FPGA configuration circuit is correct.

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Outdoor led flood light picture show:


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